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New posts in instruction-set
Differences between RISC-V and others ISAs
Nov 07, 2018
cpu-architecture
riscv
instruction-set
xorl %eax - Instruction set architecture in IA-32
Sep 15, 2022
c
assembly
x86
att
instruction-set
Determine instruction set of my processor under Linux
Nov 11, 2022
linux
processor
instruction-set
does gcc's __builtin_cpu_supports check for OS support?
Mar 24, 2021
c
gcc
simd
intrinsics
instruction-set
Do different ARM manufacturers provide different instruction sets?
Sep 24, 2022
arm
instruction-set
What EXACTLY is the difference between intel's and amd's ISA, if any?
Mar 01, 2022
x86-64
intel
amd-processor
instruction-set
MOVZX missing 32 bit register to 64 bit register
Mar 07, 2022
assembly
x86-64
instruction-set
Difference between ISA (e.g. MIPS) and Assembly language
May 10, 2022
assembly
mips
instruction-set
How does a zero register improve performance?
Apr 07, 2022
mips
cpu-registers
instruction-set
Standard C++11 code equivalent to the PEXT Haswell instruction (and likely to be optimized by compiler)
Jun 11, 2019
c++
c++11
bit-manipulation
compiler-optimization
instruction-set
intel
x86
bmi
How to use processor instructions in C++ to implement fast arithmetic operations
Dec 01, 2021
c++
assembly
processor
instruction-set
Which x86 instruction has a 10-byte immediate?
Sep 07, 2022
assembly
x86
x86-64
machine-code
instruction-set
MIPS: Why do we need load byte when we already have load word?
Nov 06, 2022
assembly
mips
instruction-set
What is an assembly-level representation of pushl/popl %esp?
Nov 03, 2022
assembly
x86
stack-memory
instruction-set
stack-pointer
How is machine code stored in the EXE file?
Nov 13, 2022
x86
portable-executable
machine-code
instruction-set
opcode
What's the point of instructions with only the REX prefix in 64bit mode?
Sep 23, 2022
assembly
x86-64
cpu-registers
instruction-set
How does the CPU know its instruction set?
Nov 19, 2022
cpu
cpu-architecture
instruction-set
machine-code
Difference between PREFETCH and PREFETCHNTA instructions
Sep 12, 2022
assembly
x86
cpu-cache
prefetch
instruction-set
Are PUSH/POP instructions considered RISC or CISC?
Oct 23, 2022
assembly
cpu-architecture
instruction-set
risc
x86 Program Counter abstracted from microarchitecture?
Mar 13, 2022
x86
cpu-architecture
riscv
instruction-set
program-counter
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