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New posts in cpu-registers

a 64-bit number does not fit in the register int in x86_64 mode

c++ c gcc assembly cpu-registers

Why the number of x86 int registers is 8?

assembly x86 x86-64 cpu-architecture cpu-registers

What is the advantage of using segment registers (today)?

assembly x86 cpu-registers memory-segmentation

Are there small registers in ARM assembly?

assembly arm cpu-registers

Need explanation about register file [closed]

cpu cpu-registers

Understanding cpu registers

linux assembly cpu cpu-registers

Running multiple processes on a single CPU

process operating-system cpu cpu-registers

how can 2 assembly programs use the same register

assembly cpu-registers

Is it valid for the Stack Pointer and Frame pointer to point to the same address in ARM 64?

assembly cpu-registers arm64 stack-frame stack-pointer

Difference between ARM ADD with 2 or 3 operands?

assembly syntax arm addition cpu-registers

In x86_64, does a 32-bit cmov clear the top bits if the condition is false?

assembly x86-64 cpu-registers conditional-move

Why Assembly x86_64 syscall parameters are not in alphabetical order like i386

assembly x86 x86-64 cpu-registers calling-convention

Performance comparison: 64 bit and 32 bit multiplication [closed]

c performance cpu cpu-registers

Meaning of XMM register values shown in Visual Studio debugger's register window

visual-studio sse visual-studio-debugging cpu-registers

Why does Windows use RCX, RDX for pointers in a fresh x64 process, different from EAX, EBX in a newly created 32-bit process?

windows assembly x86-64 32bit-64bit cpu-registers

Meaning of pc in gdb (alias?)

assembly gcc gdb cpu-registers program-counter

Are "Protection rings" and "CPU modes" the same thing?

operating-system cpu cpu-architecture cpu-registers

What's the advantage of having nonvolatile registers in a calling convention?

assembly x86-64 cpu-architecture cpu-registers calling-convention

Why do we use sub esp, 4 instead of push a register in assembly?

assembly optimization x86 stack cpu-registers

Why the %r0 of SPARC or MIPS, is always 0?

assembly mips cpu-architecture cpu-registers sparc
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