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New posts in cpu-architecture
Does clwb take care of the write in store buffer?
Sep 10, 2026
assembly
x86
x86-64
cpu-architecture
persistent-memory
Why do we even need cache coherence?
Sep 10, 2026
c
cpu
cpu-architecture
cpu-cache
Performance differ significantly when inner loop iterates less times?
Sep 09, 2026
c++
assembly
gcc
x86-64
cpu-architecture
Does anyone have an example where _mm256_stream_load_si256 (non-tempral load to bypasse cache) actually improves performance?
Sep 08, 2026
performance
x86
cpu-architecture
hpc
avx
Is movndq works?
Sep 07, 2026
c
assembly
cpu-architecture
measurement
cpu-cache
In MESI cache coherence protocol, when exactly does the state of a cache line change if the data needs to be fetched from memory?
Sep 07, 2026
cpu-architecture
cpu-cache
mesi
How computationally expensive is `exp`?
Sep 06, 2026
gpu
cpu
speech-recognition
cpu-architecture
exp
How are microcodes executed during an instruction cycle?
Sep 05, 2026
assembly
cpu
cpu-architecture
HOW TO FORCEFULLY DISABLE intel_pstate? intel_pstate is enabled on reboot even with intel_pstate=disable option in grub
Sep 05, 2026
linux
linux-kernel
cpu
intel
cpu-architecture
Latency bounds and throughput bounds for processors for operations that must occur in sequence
Sep 03, 2026
performance
cpu-architecture
micro-optimization
Double-precision operations: 32-bit vs 64-bit machines
Sep 04, 2026
performance
memory
floating-point
cpu-architecture
32bit-64bit
How much memory does my CPU support?
Sep 02, 2026
c#
.net
memory-management
32bit-64bit
cpu-architecture
Does AVX/AVX2 "exists" on each core?
Sep 02, 2026
c++
cpu-architecture
simd
avx
avx2
Can speculative execution of modern CPUs cross loop iterations?
Sep 01, 2026
assembly
x86-64
pipeline
cpu-architecture
speculative-execution
ARM vs x86; What are the key differences?
Aug 31, 2026
x86
arm
cpu
cpu-architecture
instruction-set
How to determine SSE prefetch instruction size?
Aug 30, 2026
cpu-architecture
sse
prefetch
Syntax Errors in VHDL with Case statement and Process Declarations
Aug 30, 2026
syntax-error
vhdl
cpu-architecture
representing the addi $s1, $0, 4 instruction: write down the value of the control signals
Aug 29, 2026
mips
cpu-architecture
How to convert a CPU name to a string for -march & -mtune for MinGW?
Aug 27, 2026
c++
windows
gcc
mingw
cpu-architecture
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