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New posts in cpu-architecture

What does word-size mean with greater size registers? [closed]

c assembly operating-system cpu-architecture cpu-word

C# Shared Memory - risk of CPU caching (non-volatile reads)?

c# shared-memory compiler-optimization cpu-architecture memory-barriers

Why not have separate CODE and DATA stacks

stack cpu-architecture exploit

Pointer chasing benchmark - unexpected lack of out of order execution?

c x86-64 cpu-architecture benchmarking cpu-cache

Which factors affect the needed compiler?

compilation operating-system cpu cpu-architecture instruction-set

Why is im2col-based 2d-convolution more efficient than naive SIMD-accelerated 2d-convolution?

memory floating-point conv-neural-network cpu-architecture instruction-set

AMD DE_CFG[9] documentation

security x86 cpu-architecture amd-processor

Necessity of J vs. JAL (and JR vs. JALR) in MIPS assembly

assembly mips cpu-architecture

Total Store Order and write merging in x86(-64)

architecture x86 x86-64 cpu-architecture

Why is rep movsb slow for overlapping forward memmove, and why does libc use it?

c++ performance x86 cpu-architecture memmove

Why are all IMUL µOPs dispatched to Port 1 only (on Haswell), even when multiple IMULs are executed in parallel?

assembly x86-64 cpu cpu-architecture intel

Does 8086 initiate a 1-byte code fetch when there's only 1 byte left in the prefetch queue?

x86 cpu-architecture x86-16

After enabling an interrupt via CSRRW in RISC-V, how many instructions may execute before trap entry?

cpu-architecture interrupt privileges riscv

Does the x86-64 pipeline stall on an indirect jump like JMP RAX?

assembly x86-64 intel cpu-architecture branch-prediction

Why are set cache associativity in modern day processors 8-way set associative?

caching intel cpu-architecture cpu-cache amd-processor
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