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Do modern CPU's have compression instructions

I have been curious about this for awhile since compression is used in about everything.

  • Are there any basic compression support instructions in the silicon on a typical modern CPU chip?

  • If not, why are they not included?

  • Why is this different from encryption, where some CPUs have hardware support for algorithms such as AES?

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Trevin Corkery Avatar asked Jan 29 '23 04:01

Trevin Corkery


1 Answers

They don’t have general-purpose compression instructions.

AES operates on very small data blocks, it accepts two 128 bit inputs, does some non-trivial computations on them, produces single 128 bit output. A dedicated instruction to speed up computation helps a lot.

On modern hardware, lossless compression speed is often limited by RAM latency. Dedicated instruction can’t improve speed, bigger and faster caches can, but modern CPUs already have very sophisticated multi-level caches. They work good enough for compression already.

If you need to compress many gigabits/second, there’re several standalone accelerators, but these are not parts of processors, usually standalone chips connected to PCIx. And they are very niche products because most users just don't need to compress that much data that fast.

However, modern CPUs have a lot of stuff for lossy multimedia compression. Most of them have multiple vector instruction set extensions (mmx, sse, avx), and some of these instructions help a lot for e.g. video compression use case. For example, _mm_sad_pu8 (SSE), _mm_sad_epu8 (SSE2), _mm256_sad_epu8 (AVX2) are very helpful for estimating compression errors of 8x8 blocks of 8 bit pixels. The AVX2 version processes 4 rows of the block in just a few cycles (5 cycles on Haswell, 1 on Skylake, 2 on Ryzen).

Finally, many CPUs have integrated GPUs which include specialized silicon for hardware video encoding and decoding, usually h.264, newer ones also h.265. Here's a table for Intel GPUs, AMD has separate names for encoding and decoding parts. That silicon is even more power efficient than SIMD instructions in the cores.

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Soonts Avatar answered Mar 03 '23 22:03

Soonts