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Difference between MIPS and ARM datapaths

I have just learnt MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. Both have different instruction formats, register set, etc.

Is there any difference in the data path of ARM from MIPS? because the data path involves fetching, decoding, and executing the instruction and it must be same for all Instruction Set Architectures.

I could not find the information about ARM data path from where I am reading this.

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azhar baloch Avatar asked Mar 09 '23 07:03

azhar baloch


1 Answers

The MIPS you learned is no doubt an educational one from the text books (Patterson and Hennessey). The real MIPS cores as well as the ARM cores can/do vary from core to core, you can have multiple armv7-m cores that have a different implementation with respect to the pipeline stages. Note ARM and MIPS and RISC in general are not microcoded, dont allow x86 implementations affect your understanding.

So there is no one answer to this, and there is no one answer to what datapaths do MIPS processors use, what datapaths do ARM processors use with respect to fetch, decode, execute, writeback, ...

The CONCEPTS fetch, decode, execute, ... are used by all processors RISC or not, just how and when they do it varies, they can break down those steps into smaller steps and implement those in a longer pipe, or do them parallel and have a wider pipe.

For MIPS anything go to MIPS and download their documentation. for arm go to arm you want the architectural reference manual and the technical reference manual for a particular architecture family and specific core you are interested in. They have some new programmers manual or developers manual, skip that, or understand it is the above two manuals with holes in it. You may also want to get the amba/axi documentation to understand how the busses work, you could design an arm with a different bus, but it is educational if you were taught the traditional address bidirectional data, writes strobe, read strobe, chip enable type bus (which still lives on in wishbone a popular bus used in open cores and other places, a little more complicated but much closer to the old school bus).

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old_timer Avatar answered Mar 15 '23 05:03

old_timer