Questions
Linux
Laravel
Mysql
Ubuntu
Git
Menu
HTML
CSS
JAVASCRIPT
SQL
PYTHON
PHP
BOOTSTRAP
JAVA
JQUERY
R
React
Kotlin
×
Linux
Laravel
Mysql
Ubuntu
Git
New posts in cpu-architecture
How does kernel know physical memory base address?
Oct 28, 2025
linux
linux-kernel
kernel
cpu-architecture
ram
Flynn's Bottleneck - maximum speedup 2
Oct 28, 2025
cpu-architecture
Bottleneck when using indexed addressing modes
Oct 27, 2025
x86-64
intel
cpu-architecture
micro-optimization
addressing-mode
What is the difference between pipeline and lane in terms of CPU architecture?
Oct 29, 2025
gpu
cpu-architecture
simd
Is uops.info wrong about vinserti128?
Oct 28, 2025
assembly
x86
cpu-architecture
simd
avx2
Which type of assembler jump instruction is most useful?
Oct 26, 2025
assembly
cpu-architecture
low-level
Temporality of ST64B and MOVDIR64B
Oct 28, 2025
assembly
x86-64
cpu-architecture
arm64
micro-architecture
Why is my benchmark using __mm_prefetch slower?
Oct 27, 2025
c++
x86
cpu-architecture
prefetch
How can Intel and AMD be different but still compatible?
Oct 27, 2025
optimization
x86
intel
cpu-architecture
amd-processor
Would an Instruction Set Architecture benefit from both an ADC and SBC, or could all carry instructions repeat the previous type?
Oct 25, 2025
assembly
cpu-architecture
instruction-set
carryflag
Why is program counter incremented by 1 if memory organised as word and by 2 in case of bytes?
Oct 25, 2025
assembly
memory
cpu-architecture
Why unlamination of μops necessary?
Oct 26, 2025
x86
cpu
intel
cpu-architecture
Reading Current Uncore Frequency and Setting Uncore Frequency Multipliers
Oct 24, 2025
x86
intel
cpu-architecture
msr
Why is acquire semantics only for reads, not writes? How can an LL/SC acquire CAS take a lock without the store reordering with the critical section?
Oct 24, 2025
assembly
cpu-architecture
stdatomic
compare-and-swap
spinlock
ARM: Why only 12 bits for immediate constants?
Oct 23, 2025
assembly
arm
cpu-architecture
instruction-set
immediate-operand
Pipeline diagram, Can ID start if previous EX is using same register?
Oct 24, 2025
architecture
mips
pipeline
cpu-architecture
Does processor stall during cache coherence operation
Oct 24, 2025
multithreading
caching
cpu-architecture
cpu-cache
Why is branch prediction quite accurate?
Oct 23, 2025
cpu
cpu-architecture
branch-prediction
Is it possible to perform some computations within the RAM?
Oct 24, 2025
assembly
x86
cpu-architecture
Calculating average time for a memory access
Oct 23, 2025
performance
memory
computer-science
cpu-architecture
cpu-cache
« Newer Entries
Older Entries »