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New posts in cpu-architecture

Can a page fault handler generate more page faults?

linux operating-system cpu-architecture tlb page-fault

Cache Implementation in Pipelined Processor

mips cpu-architecture cpu-cache

What does it mean by a branch penalty?

assembly cpu-architecture branch-prediction

What is the difference between "soft reset" and "hard reset" in embedded field?

embedded cpu-architecture reset motherboard chipset

boost lockfree spsc_queue cache memory access

memory boost cpu-architecture lock-free cpu-cache

Why isn't movl from memory to memory allowed?

assembly x86 cpu-architecture instruction-set

256 bit fixed point arithmetic, the future?

performance floating-point precision cpu-architecture fixed-point

According to Intel my cache should be 24-way associative though its 12-way, how is that?

performance intel cpu-architecture cpu-cache micro-optimization

Can two instructions execute in the same cycle if the same register is used as input and output respectively?

assembly x86 x86-64 cpu-architecture micro-optimization

What is the purpose of the reserved/undefined bit in the flag register?

cpu-architecture x86-16 z80 8085 intel-8080

Would buffering cache changes prevent Meltdown?

caching x86 cpu cpu-architecture cpu-cache

Is a mov to a segmentation register slower than a mov to a general purpose register?

assembly x86 cpu-architecture memory-segmentation cpu-cycles

How to use XACQUIRE, XRELEASE Hardware Lock Elision (HLE) prefix hints?

assembly x86 x86-64 intel cpu-architecture

Is test-and-set (or other atomic RMW operation) a privileged instruction on any architecture?

linux assembly operating-system cpu-architecture futex

Does Cache empty itself if idle for a long time?

cpu-architecture cpu-cache

Do any CPU architectures use Metadata?

cpu-architecture

Are caches of different level operating in the same frequency domain?

caching cpu cpu-architecture

Conditional jump instructions in MSROM procedures?

x86 intel cpu-architecture branch-prediction micro-architecture

How does a return address register work in a processor architecture that doesn't store the return address on the stack?

assembly cpu-architecture

Does hardware consolidate multiple code operations into one physical CPU operation?

c++ c optimization cpu-architecture cpu-cache
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