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New posts in micro-optimization

Insert a bit in a byte at pos n with Assembly

assembly arm micro-optimization cortex-m

Is it faster to pop unneeded values from the stack, or add an immediate constant to SP on a 386+ CPU?

performance assembly stack x86-16 micro-optimization

Branchless count-leading-zeros on 32-bit RISC-V without Zbb extension

algorithm bit-manipulation riscv micro-optimization riscv32

Missing optimization: mov al, [mem] to bitfield-insert a new low byte into an integer

c assembly x86-64 micro-optimization

Intel 8086 Assembly -- Squaring a Register

assembly micro-optimization x86-16

C++ Is this a form of micro optimization

c++ micro-optimization

Does each Floating point operation take the same time?

performance floating-point cpu-architecture micro-optimization alu

What is faster in C++: mod (%) or another counter?

c++ performance assembly micro-optimization branch-prediction

Which sequence of instructions has better performance for zeroing one register or another?

performance assembly mips cpu-architecture micro-optimization

When source registers in avx instruction can be reused

assembly cpu-architecture simd avx micro-optimization

Using Intrinsics to Extract And Shift Odd/Even Bits

c++ bit-manipulation intrinsics micro-optimization

Should I aggressively release memory while reading a file line by line in Perl?

perl memory-management micro-optimization

Long latency instruction

optimization x86 cpu-architecture micro-optimization microbenchmark

Why is this reordering of sub and mul instructions helpful?

c assembly gcc cpu-architecture micro-optimization

3D Morton code computation utilizing carry-less multiplication

algorithm assembly bit-manipulation riscv micro-optimization

x86 assembly - optimization of clamping rax to [ 0 .. limit )

assembly optimization x86 micro-optimization clamp

Why does some Windows booloader code zero registers with `sub` instead of `xor`?

assembly x86 micro-optimization zero-initialization

Does it make sense to use a relaxed load followed by a conditional fence, if I don't always need acquire semantics?

c++ multithreading atomic micro-optimization memory-barriers
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