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New posts in micro-architecture

Will CPUID serialize speculative data caching?

x86 cpu-cache microbenchmark cpuid micro-architecture

Temporality of ST64B and MOVDIR64B

assembly x86-64 cpu-architecture arm64 micro-architecture

Architecture and microarchitecture

system cpu cpu-architecture micro-architecture

how do i get the cpu information for my computer i.e functional units/latency etc

assembly x86 cpu-architecture micro-architecture

Intel JCC Erratum - should JCC really be treated separately?

assembly x86 intel cpu-architecture micro-architecture

How modern X86 processors actually compute multiplications?

algorithm x86 cpu-architecture alu micro-architecture

How is the transitivity/cumulativity property of memory barriers implemented micro-architecturally?

x86 x86-64 cpu-architecture memory-barriers micro-architecture

Conditional jump instructions in MSROM procedures?

x86 intel cpu-architecture branch-prediction micro-architecture

Why jnz requires 2 cycles to complete in an inner loop

x86 micro-optimization microbenchmark micro-architecture

What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?

cuda gpu gpgpu micro-architecture nsight-compute

Are load ops deallocated from the RS when they dispatch, complete or some other time?

x86 intel cpu-architecture micro-architecture

How to tell length of an x86-64 instruction opcode using CPU itself?

x86 x86-64 cpu-architecture opcode micro-architecture

Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?

assembly x86 micro-optimization microbenchmark micro-architecture

How do the store buffer and Line Fill Buffer interact with each other?

x86 cpu-architecture cpu-cache micro-architecture cpu-mds

Does memory dependence speculation prevent BN_consttime_swap from being constant-time?

c assembly openssl constant-time micro-architecture
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