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New posts in micro-architecture
How modern X86 processors actually compute multiplications?
Mar 21, 2023
algorithm
x86
cpu-architecture
alu
micro-architecture
How is the transitivity/cumulativity property of memory barriers implemented micro-architecturally?
Mar 04, 2023
x86
x86-64
cpu-architecture
memory-barriers
micro-architecture
Conditional jump instructions in MSROM procedures?
Dec 25, 2022
x86
intel
cpu-architecture
branch-prediction
micro-architecture
Why jnz requires 2 cycles to complete in an inner loop
Feb 07, 2021
x86
micro-optimization
microbenchmark
micro-architecture
What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?
Nov 16, 2021
cuda
gpu
gpgpu
micro-architecture
nsight-compute
Are load ops deallocated from the RS when they dispatch, complete or some other time?
Apr 23, 2022
x86
intel
cpu-architecture
micro-architecture
How to tell length of an x86-64 instruction opcode using CPU itself?
Aug 22, 2022
x86
x86-64
cpu-architecture
opcode
micro-architecture
Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
Jun 21, 2021
assembly
x86
micro-optimization
microbenchmark
micro-architecture
How do the store buffer and Line Fill Buffer interact with each other?
Aug 26, 2022
x86
cpu-architecture
cpu-cache
micro-architecture
cpu-mds
How does the indexing of the Ice Lake's 48KiB L1 data cache work?
Nov 09, 2020
x86
intel
cpu-architecture
cpu-cache
micro-architecture
Any reason to use BX R over MOV pc, R except thumb interwork pre ARMv7?
Feb 25, 2022
assembly
arm
cpu-architecture
branch-prediction
micro-architecture
how are barriers/fences and acquire, release semantics implemented microarchitecturally?
Nov 07, 2022
x86
x86-64
cpu-architecture
memory-barriers
micro-architecture
Adding a redundant assignment speeds up code when compiled without optimization
Aug 10, 2021
performance
assembly
x86
cpu-architecture
micro-architecture
Return stack buffer?
Feb 20, 2020
x86
cpu
cpu-architecture
branch-prediction
micro-architecture
Why isn't there a data bus which is as wide as the cache line size?
Apr 08, 2022
caching
memory
cpu-architecture
cpu-cache
micro-architecture
Does memory dependence speculation prevent BN_consttime_swap from being constant-time?
Jan 30, 2022
c
assembly
openssl
constant-time
micro-architecture
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