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New posts in micro-architecture

What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?

cuda gpu gpgpu micro-architecture nsight-compute

Are load ops deallocated from the RS when they dispatch, complete or some other time?

x86 intel cpu-architecture micro-architecture

How to tell length of an x86-64 instruction opcode using CPU itself?

x86 x86-64 cpu-architecture opcode micro-architecture

Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?

assembly x86 micro-optimization microbenchmark micro-architecture

How do the store buffer and Line Fill Buffer interact with each other?

x86 cpu-architecture cpu-cache micro-architecture cpu-mds

How does the indexing of the Ice Lake's 48KiB L1 data cache work?

x86 intel cpu-architecture cpu-cache micro-architecture

Any reason to use BX R over MOV pc, R except thumb interwork pre ARMv7?

assembly arm cpu-architecture branch-prediction micro-architecture

how are barriers/fences and acquire, release semantics implemented microarchitecturally?

x86 x86-64 cpu-architecture memory-barriers micro-architecture

Adding a redundant assignment speeds up code when compiled without optimization

performance assembly x86 cpu-architecture micro-architecture

Return stack buffer?

x86 cpu cpu-architecture branch-prediction micro-architecture

Why isn't there a data bus which is as wide as the cache line size?

caching memory cpu-architecture cpu-cache micro-architecture

What are my available march/mtune options?

gcc command-line x86 compiler-flags micro-architecture intel
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