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New posts in memory-model

8/16-bit atomics on 32/64-bit processors

what orderings are guaranteed by the ARM weak memory model

arm multicore memory-model

Fence instruction insertion by JVM/JIT

Race condition in Morris's algorithm

Does STLR(B) provide sequential consistency on ARM64?

Are all side-effects of executor tasks visible after invokeAll?

Does statement re-ordering apply to conditional/control statements?

atomic<T>.load() with std::memory_order_release

When can I guarantee value changed on one thread is visible to other threads?

The strong-ness of x86 store instruction wrt. SC-DRF?

x86_64 memory reorder

Why can't you use relaxed atomic operations to synchronize memory, if there is a thread join in between?

Transitivity of release-acquire

boost vs std atomic sequential consistency semantics

Reorder relaxed atomic operations on the same object

Can the C++ compiler coalesce adjacent mutex locks?

Reordering External Operations in Java Memory Model