Differences between RISC-V and others ISAs

Question

Can someone explain to me the big differences between ( RISC vs CISC ) vs the RISC-V ISA? I cannot find any relevant difference between CISC and RISC-V on the internet.

Answer 1

RISC-V is a new ISA developed at Berkeley to assist in both research and education. It is open, clean, and easily extensible (and also realistic).

A common problem with building research processors is finding an ISA to use that isn't muddled with legacy decisions (delay slots, register windows), isn't protected by patents, and has enough opcode space to explore new instructions/accelerators/processor micro-architectures.

A public release (v2.0) is coming soon, and you can read the current draft at riscv.org. (disclosure: I use RISC-V for my own research, and I sit next to the guys who designed and implemented it). [Edit: It has been officially released as of May 2014 (http://riscv.org/download.html#tab_isaspec)].

In terms of comparison to other ISAs, it is probably most similar to MIPS and ARMv8 (RISC-V v1.0 was actually released before ARMv8 came out). It is a load-store architecture (no register-memory operations like x86, except for a set of AMOs). There are some parts of RISC-V that you could argue is "CISC-y", like the option to support compressed instructions for energy reasons (16b) or larger instructions for even more opcode space (variable instruction length is an optional superset, the base-set of the ISA is all 32b instructions). Also FMAs feel a bit CISC-y too, with three source operands and two operations. But now we're meandering into opinion territory of what's CISC and what's RISC. At the end of the day, RISC-V is a very easy to decode ISA, and all instructions in it are easy to schedule and do hazard checking on (no weird side-effects, as you would find in CISC ISAs).