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If I understand these two articles, the Intel architecture, at it's lowest level, has transitioned to using RISC instructions, instead of the the traditional CISC instruction set that Intel is known for:
http://www.hardwaresecrets.com/article/235/4
http://www.tomshardware.com/reviews/intel,264-6.html
If that's the case, then are x86/x64 chips still microprogrammed or does it use hardwired control like traditional RISC chips? I'm going to guess it's still microprogrammed but wanted to verify.
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asked Mar 01 '10 04:03
Starting with the Pentium Pro in 1995, several x86 CPUs have writable Intel Microcode. This, for example, has allowed bugs in the Intel Core 2 and Intel Xeon microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced.
Microprogramming is used for making control units of such processors, because it is far less complex and can be easily modified. Modern high level languages have more advanced and complex data types. Microprogramming can provide support for such data types directly from the processor level.
Intel microcode is microcode that runs inside x86 processors made by Intel. Since the P6 microarchitecture introduced in the mid-1990s, the microcode programs can be patched by the operating system or BIOS firmware to work around bugs found in the CPU after release.
Micro programs are the components of all computer microprocessors that do not get altered once control units are in operation. Therefore, all micro programmed computers are microprocessors.
Microcode has been around for a long time, if that's what you're referring to. So I don't know what the HardwareSecrets article is on about, unless Intel is now building RISC processors on top of CISC processors.
Even the HardwareSecrets article calls them Micro-Instructions. Potato, potahto.
http://en.wikipedia.org/wiki/Microcode
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On modern x86 processors, most instructions execute without microcode (*), but some complex or infrequently executed ones do use microcode.
(*) Not to be confused with micro-ops -- in x86 out-of-order processors, x86 instructions are typically decoded into one or more micro-ops which then are queued for execution (sans microcode!) in the out-of-order execution pipeline.
It is also interesting to note that modern x86 processors have a facility to patch/update microcode in order to fix errata in the field.
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