Are PUSH/POP instructions considered RISC or CISC?

Question

I was asked in an interview if PUSH and POP are RISC or CISC instructions. I said that they were RISC, but they told me that they were actually CISC instructions. I suggested that ARM (a common RISC implementation) has these instructions, but they pointed out that ARM is mixed and not purely RISC anymore.

I can't find any definitive proof one way or the other online. Are PUSH and POP instructions really considered a hallmark of a CISC architecture, or would they be found on a RISC system? Why?

Answer 1

RISC means "reduced instruction set" (typically LOAD reg, STORE register, ADD register, CMP register, Branch conditional + a few others).

The notion, and experience, is that complex instructions often do not achieve a useful effect that cannot be achieved by simpler instruction sequences, especially if the extra logic that would be used to implement such complex instructions is instead invested in making the simple RISC instructions run faster.

PUSH and POP are basically simple combinations of STORE/LOAD indirect, and ADD a constant to a register. So if one dedicates register for a stack pointer, PUSH and POP are easily simulated and a fast pipelined machine can probably execute PUSH and POP about as fast as the corresponding RISC instructions. So most consider PUSH and POP to be CISC instructions; they don't really buy you a lot.

Life gets more interesting if you consider CALL (== PUSH PC + JMP) and RET (POP PC). These are also easy to simulate on the right RISC architecture. However, POP PC incurs a pipeline bubble because the processor has a hard time predicting where the new PC will be, and so can't do a prefetch. With memory being "far away in time", this can be a major performance inhibitor in code with lots of subroutine calls.

Here, one sort of wants to go CISC. What you really want is some way to predict that return PC. Many modern CPUs do this by keeping a "shadow call stack" in the hardware. Each CALL pushes the PC into the memory stack, and also onto the shadow stack; each RET pops a PC value from the memory stack, but predicts instruction stream flow using the top entry of the shadow stack which it has essentially zero-time access to (and of course, pops the shadow stack). This way the instruction stream doesn't get interrupted, and the CISC machine thus wins on performance.

(One wonders if a RISC machine with lots of registers, that compiled leaf function calls to always use a register to store the return PC, might not be as effective as a shadow stack. Sun Sparc sort of does this with its register window).

What this tells us is that RISC vs. CISC oversimplifies the design tradeoff. What you want is simple, unless more complexity actually buys you something. For example, IEEE floating-point in hardware is lots faster than any simulation using RISC instructions.

As a consequence, most modern machines are not neatly RISC or CISC. Performance profiling chooses.

Answer 2

"RISC" means different things to different people. Definitions I've seen include:

• a reduced number of instructions

• fixed size instructions (possibly lots of them)

• a load/store architecture (possibly with lots of variable sized instructions)

• a CPU that doesn't translate instructions into micro-ops and doesn't have "micro-code" (e.g. 8086, 8088, 80186, ..., but not 80486, Pentium, ...)

• any combination of 2 or more of the things above

• anything that sacrifices performance for the sake of reducing development costs

Are PUSH/POP instructions considered RISC or CISC?

Yes (PUSH/POP instructions are considered RISC, or CISC, or both, or neither; depending on which definition of RISC or CISC is being applied when).

Mostly the question itself is a false dichotomy; like asking "is grey black or white?".