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New posts in x86

All asm labels becoming symbols in executable file

assembly linker x86 nasm elf

Find the first instance of a character using simd

x86 sse simd avx avx2

Can and does the compiler optimize out two atomic loads? [duplicate]

c++ gcc x86 atomic compiler-optimization

conditional jumps -- comparing c code to assembly

c assembly x86

Can I pop from the middle of a stack?

assembly x86 callstack abi red-zone

Does a zero change jump on x86 clear the instruction prefetch queue?

assembly x86

When should I use size directives in x86?

assembly x86 x86-64 directive

how to get address of variable and dereference it in nasm x86 assembly?

pointers assembly x86 nasm

How does xchg work in Intel Assembly Language

assembly x86

What does __asm volatile ("pause" ::: "memory"); do?

c++ assembly parallel-processing x86 inline-assembly

How to tell length of an x86-64 instruction opcode using CPU itself?

x86 x86-64 cpu-architecture opcode micro-architecture

How do I link a C++ subroutine to an x86 assembly program?

c++ gcc assembly x86 nasm

How do Intel CPUs that use the ring bus topology decode and handle port I/O operations

io x86 intel hardware cpu-architecture

AVX2 instructions latency and throughput

performance x86 x86-64 simd avx2

How to properly setup SS, BP and SP in x86 Real Mode?

assembly x86 callstack bios

Is it worse in any aspect to use the CMPXCHG instruction on an 8-bit field than on a 32-bit field?

c assembly x86 c11 instruction-set

What does 'REX' stand for in an x86-64 REX prefix?

assembly x86 x86-64 intel machine-code

Why BIOS need to compare a value in (seemly) randomized address to zero in the second instruction?

assembly x86 qemu bios osdev

Optimizing an incrementing ASCII decimal counter in video RAM on 7th gen Intel Core

assembly optimization x86 intel bootloader

Where to get the I/O port addresses assignment for hardware?

assembly io x86 hardware
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