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New posts in x86

Interpreting GDB registers (SSE registers)

unix x86 gdb sse

What does this instruction do ( REP MOVS BYTE PTR ES:[EDI],BYTE PTR DS: )?

assembly x86 instructions

Subtracting registers with an LEA instruction?

assembly x86 x86-64 pointer-arithmetic addressing-mode

How does this sqrt approximation inline assembly function work?

assembly optimization x86 square-root sar

Do compilers usually use registers for their "intended" purpose?

assembly compilation compiler-construction x86 x86-64

ADC instruction in asm

assembly x86 cpu-registers carryflag

Can an instruction be in two addressing modes at the same time?

assembly x86 addressing-mode

Why isn't my root directory being loaded? (FAT12)

assembly x86 nasm bootloader fat

How does "+&r" differ from "+r"?

c gcc x86 inline-assembly

x86 Assembly: Data in the Text Section

assembly x86 shellcode

Do locked instructions provide a barrier between weakly-ordered accesses?

multithreading x86 intel memory-model memory-fences

Why is L1 write access access worst with two threads in the same core (hyperthreading) than two cores?

c++ multithreading x86

Pipeline on Registers calculation

c++ assembly x86 cpu-architecture

How to optimize DivMod for a constant divisor of 10

delphi x86 inline-assembly micro-optimization

Are load ops deallocated from the RS when they dispatch, complete or some other time?

x86 intel cpu-architecture micro-architecture

Why does int addition though pointers take one less x86 instruction than int multiplication through pointers?

c++ pointers assembly x86 instruction-set

Configure ASP.NET to use x86 on x64 Windows

asp.net ms-access x86 jet windows64

How can I explain the behavior of the following shellcode exploit?

assembly x86 buffer-overflow exploit shellcode

Process Page Tables

c windows assembly x86 kernel

Confusion with how Win32 API calls work in assembly

windows winapi assembly x86 nasm
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