Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in cpu-architecture

Detecting CPU architecture (32bit / 64bit ) in scons?

build-process scons cpu-architecture

what is difference between 32 bit vs 64 bit OSs and processors (Intel architecture and WIndows)

operating-system cpu-architecture

Can i use the same ARM assembly for different ARM processors (Cortex,Tegra and so on)?

assembly arm cpu-architecture instruction-set

Why are bgezal & bltzal basic instructions and not pseudo-instructions in MIPS?

assembly mips cpu-architecture

Where does the instruction of an executable go to?

operating-system system-calls cpu-architecture

What percentage of Android phones are little-endian?

java android cpu-architecture endianness

Are cache operations atomic?

assembly intel cpu-architecture cpu-cache mesi

Branch prediction overhead of perfectly predicted branch

c++ performance x86 cpu-architecture branch-prediction

Do modern CPU's have compression instructions

cpu-architecture instructions

Can a page fault handler generate more page faults?

linux operating-system cpu-architecture tlb page-fault

Cache Implementation in Pipelined Processor

mips cpu-architecture cpu-cache

What does it mean by a branch penalty?

assembly cpu-architecture branch-prediction

What is the difference between "soft reset" and "hard reset" in embedded field?

embedded cpu-architecture reset motherboard chipset

boost lockfree spsc_queue cache memory access

memory boost cpu-architecture lock-free cpu-cache

Why isn't movl from memory to memory allowed?

assembly x86 cpu-architecture instruction-set

256 bit fixed point arithmetic, the future?

performance floating-point precision cpu-architecture fixed-point

According to Intel my cache should be 24-way associative though its 12-way, how is that?

performance intel cpu-architecture cpu-cache micro-optimization

Can two instructions execute in the same cycle if the same register is used as input and output respectively?

assembly x86 x86-64 cpu-architecture micro-optimization

What is the purpose of the reserved/undefined bit in the flag register?

cpu-architecture x86-16 z80 8085 intel-8080

If I don't use fences, how long could it take a core to see another core's writes?

x86 intel cpu-architecture memory-barriers lockless
« Newer Entries Older Entries »