Compulsory miss occurs when the block is brought first time into the cache.
Conflict miss in the case of set associative or direct mapped block placement strategies, conflict misses occur when several blocks are mapped to the same set.
Consider a 2 - way set associative cache memory with 4 sets and total 8 cache blocks (0 - 7) .Main memory has 64 blocks (0 - 63). If LRU policy is used for replacement and cache is initially empty then total number of conflict cache misses for the following sequence of memory block references is : 0 5 9 13 7 0 15 25
My doubt is, will 13 and 25 cause only compulsory miss or compulsory & conflict miss both?
Conflict Miss – It is also known as collision misses or interference misses. These misses occur when several blocks are mapped to the same set or block frame. These misses occur in the set associative or direct mapped block placement strategies.
Capacity misses occur when the cache is too small to hold all concurrently used data. Conflict misses are caused when several addresses map to the same set and evict blocks that are still needed. Changing cache parameters can affect one or more types of cache miss.
Compulsory miss occurs when the block is brought first time into the cache. Conflict miss in the case of set associative or direct mapped block placement strategies, conflict misses occur when several blocks are mapped to the same set.
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Your definition of a "conflict miss" is a bit unhelpful.
A conflict miss occurs when a block is needed which existed in the cache before, but was evicted in favor of another block that had to be mapped to the same slot.
In your example, the accesses to 13 and 25 are unique, so they are necessarily first accesses. They cannot have been evicted before the first use, by definition. Hence, they're compulsory misses.
They may cause subsequent conflict misses (and capacity misses), of course.
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