Can atomic instructions straddle cache lines?

Question

Can x86 instructions like LOCK DEC straddle multiple cache lines, or will they seg-fault?

Not asking if they should, just whether its allowed.

(I know certain SSE instructions must be aligned on cache boundaries)

Answer 1

Yes it's allowed. You could have also just tried it. Or read the instruction set reference:

The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.

But see also:

Exceptions

#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Note that alignment checking is not usually enabled.