Why does ARM distinguish between SDIV and UDIV but not with ADD, SUB and MUL?

Question

As stated in the title, why does the ARM instruction set distinguish between signed and unsigned only on division?

SDIV and UDIV are available but that's not the case with ADD, SUB and MUL.

Answer 1

addition and subtraction of signed and unsigned numbers of the same size produce exactly the same bit patterns in two's complement math (which ARM uses), so there is no need for separate instructions.

For example, if we take byte-sized values:

0xFC +4 
signed: -4+4 = 0
unsigned: 252 +4 = 256 = 0x100 = 0x00 (truncated to byte)

Multiplication result does change depending on whether the operands are interpreted as signed or unsigned, however the MUL instruction produces only the low 32 bits of the result, which are the same in both cases. In recent ARM processors there are instructions which produce the full 64-bit result, and those come in pairs just like SDIV and UDIV: UMULL, UMLAL, SSMULL, SMLAL:

Signed and Unsigned Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.