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New posts in intel-pmu
PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE concurrent monitoring
Oct 17, 2022
perf
multiplexing
intel-pmu
Is it possible for the RESOURCE_STALLS.RS event to occur even when the RS is not completely full?
Jul 05, 2022
performance
x86
intel
cpu-architecture
intel-pmu
Can we measure successful store-forwarding with Intel's performance counters?
Apr 18, 2022
performance
x86
intel-pmu
Why are the user-mode L1 store miss events only counted when there is a store initialization loop?
Nov 06, 2021
x86
intel
performancecounter
cpu-cache
intel-pmu
Hardware cache events and perf
Jun 07, 2022
linux
performance
x86
perf
intel-pmu
rdpmc: surprising behavior
Oct 13, 2021
performance
assembly
x86
performancecounter
intel-pmu
Can the LSD issue uOPs from the next iteration of the detected loop?
Feb 21, 2021
assembly
x86
cpu-architecture
intel-pmu
Why does the number of uops per iteration increase with the stride of streaming loads?
Jan 01, 2022
assembly
x86
cpu-architecture
intel-pmu
Reliability of Xcode Instrument's disassembly time profiling
Oct 22, 2022
xcode
x86
profiling
instruments
intel-pmu
What is the overhead of using Intel Last Branch Record?
Apr 02, 2022
x86
intel
trace
branch-prediction
intel-pmu
Can the Intel performance monitor counters be used to measure memory bandwidth?
Nov 05, 2022
performance
x86
intel-pmu
memory-bandwidth
Haswell memory access
Sep 12, 2022
performance
x86
cpu-architecture
avx2
intel-pmu
What restriction is perf_event_paranoid == 1 actually putting on x86 perf?
Dec 09, 2021
linux-kernel
x86
profiling
perf
intel-pmu