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New posts in intel-pmu

PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE concurrent monitoring

perf multiplexing intel-pmu

Is it possible for the RESOURCE_STALLS.RS event to occur even when the RS is not completely full?

Can we measure successful store-forwarding with Intel's performance counters?

performance x86 intel-pmu

Why are the user-mode L1 store miss events only counted when there is a store initialization loop?

Hardware cache events and perf

rdpmc: surprising behavior

Can the LSD issue uOPs from the next iteration of the detected loop?

Why does the number of uops per iteration increase with the stride of streaming loads?

Reliability of Xcode Instrument's disassembly time profiling

What is the overhead of using Intel Last Branch Record?

Can the Intel performance monitor counters be used to measure memory bandwidth?

Haswell memory access

What restriction is perf_event_paranoid == 1 actually putting on x86 perf?