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New posts in cpu-architecture

Would buffering cache changes prevent Meltdown?

caching x86 cpu cpu-architecture cpu-cache

Is a mov to a segmentation register slower than a mov to a general purpose register?

assembly x86 cpu-architecture memory-segmentation cpu-cycles

How to use XACQUIRE, XRELEASE Hardware Lock Elision (HLE) prefix hints?

assembly x86 x86-64 intel cpu-architecture

Is test-and-set (or other atomic RMW operation) a privileged instruction on any architecture?

linux assembly operating-system cpu-architecture futex

Does Cache empty itself if idle for a long time?

cpu-architecture cpu-cache

Do any CPU architectures use Metadata?

cpu-architecture

Are caches of different level operating in the same frequency domain?

caching cpu cpu-architecture

Conditional jump instructions in MSROM procedures?

x86 intel cpu-architecture branch-prediction micro-architecture

How does a return address register work in a processor architecture that doesn't store the return address on the stack?

assembly cpu-architecture

Does hardware consolidate multiple code operations into one physical CPU operation?

c++ c optimization cpu-architecture cpu-cache

Is CPU access asymmetric to Network card

performance networking cpu-architecture

Which is faster for bitwise NOT operation: precalculated table or `~`

c++ cpu-architecture cpu-cache micro-optimization

How to force cpu core to flush store buffer in c?

c multithreading x86 cpu-architecture cpu-cache

Why any modern x86 masks shift count to the 5 low bits in CL

assembly x86 cpu-architecture bit-shift cpu-registers

Do certain languages have intrinsic processor architectures by-design

programming-languages cpu-architecture

why we can't move a 64-bit immediate value to memory?

assembly x86-64 cpu-architecture instruction-set immediate-operand

Why misaligned address access incur 2 or more accesses?

performance cpu cpu-architecture computer-architecture

Can out-of-order execution lead to speculative memory accesses?

x86 arm cpu-architecture powerpc sparc

Can a speculatively executed CPU branch contain opcodes that access RAM?

cpu cpu-architecture speculative-execution

Convert object file to another architecture

linux x86 arm cpu-architecture
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