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New posts in verilog
Is there a ifx-elsex statement in Verilog/SV like casex?
Mar 26, 2023
verilog
system-verilog
Do all Flip Flops in a design need to be resettable (ASIC)?
Mar 19, 2023
vhdl
verilog
system-verilog
asic
Why do we use Blocking statement in Combinatorial Circuits designed using Always Block in Verilog/Systemverilog ? Why not Nonblocking?
Mar 15, 2023
verilog
fpga
system-verilog
synthesis
register-transfer-level
Verilog (assign in always)
Mar 11, 2023
verilog
what are the uses of case 'inside's in verilog ? is it synthesizable?
Mar 06, 2023
verilog
system-verilog
How do I get rid of sensitivity list warning when synthesizing Verilog code?
Mar 02, 2023
verilog
synthesis
VHDL/Verilog: access HDMI port [closed]
Feb 21, 2023
vhdl
verilog
fpga
xilinx
hdmi
Problems with wires declared inside verilog generate blocks
Feb 16, 2023
declaration
verilog
' Illegal output or inout port ' error when trying to simulate counter
Feb 15, 2023
verilog
Fill 0's with 1's beetween two 1's (synthesizable)
Feb 14, 2023
verilog
system-verilog
Difference between behavioral and dataflow in verilog
Feb 13, 2023
verilog
FSM export using Yosys
Feb 11, 2023
verilog
fsm
yosys
System Verilog - case with or
Feb 07, 2023
case
verilog
system-verilog
Shift Registers Verilog
Jan 24, 2023
verilog
vlsi
24 bit counter state machine
Jan 21, 2023
verilog
fpga
combinatorial hardware multiplication in verilog
Jan 21, 2023
hardware
verilog
synthesis
Testing my HDL Code (Verilog/VHDL) without an FPGA?
Jan 17, 2023
testing
vhdl
verilog
register-transfer-level
hdl
Incrementing a counter variable in verilog: combinational or sequential
Jan 17, 2023
hardware
verilog
fpga
sequential
How do I install GTKWave on Windows?
Jan 14, 2023
gtk
vhdl
verilog
simulator
what is this error "invalid module item" in verliog?
Jan 15, 2023
verilog
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