combinatorial hardware multiplication in verilog

Question

Suppose I have a multiplier code like this,

      module multiply(
        output [63:0] result,
        input [31:0] a,
        input [31:0] b
      );

        assign result = a * b;

      endmodule

This produces a lot of gates.

What preferable method should be used to implement combinatorial multiplier?

Answer 1

Hardware multipliers are big, you just have to live with it!

Multipliers will get bigger as its input bit widths get bigger. So if you don't need the full 32 bits on one of you operands, then reducing this size to the minimum will reduce the size of the resulting hardware.

If you're multiplying by a fixed number, I think the compiler can make some optimizations to limit the size of the hardware too. Or you can use different encoding schemes for the fixed number such as CSD that will reduce the number of adders in the multiplier, further reducing its area.

If you need loads of multipliers and have a fast clock, maybe you can reuse a single hardware multiplier for many calculations. This means writing some control/pipelining logic to schedule your multiplies, and you might need some memory, but it can save you area overall. You'd be designing a mini-DSP datapath in this case.

Answer 2

If you can forgo the combinatorial requirement, you can do multiplication using an adder and an accumulator, if speed isn't a large concern and you're able to process the operands over multiple clocks. Some low power/low cost/small area processors don't have dedicated multiply instructions in their ISA, or the multiply asm instruction is changed into addition operations by the front-end instruction decoder into addition microcode operations.

If you were to use this methodology, you'd have to create additional signals for the data hand-shake, since the output is no longer valid 1 cycle after the input settles.