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New posts in yosys

iCE40 IceStorm FPGA Flow: Bi-directional IO pins

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FSM export using Yosys

verilog fsm yosys

How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools

verilog yosys ice40

What is required to target a new device?

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What is a good "template" Yosys synthesis script?

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iCEstick + yosys - using the Global Set/Reset (GSR)

fpga yosys

How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?

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Is it possible to create a simulation waveform from yosys output

verilog simulation fpga yosys