iCE40 IceStorm FPGA Flow: Bi-directional IO pins

Question

Using the iCE40 FOSS IceStorm FPGA flow: how does one write Verilog for a 3-state I/O pin (like a bidirectional data bus pin) using yosys/iceStorm?

Answer 1

Currently there is only limited support for inferring nontrivial IO buffers from behavioral code. So the best way of creating bidirectional IO buffers is by manually instantiating an SB_IO cell. For example:

SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
) raspi_io [8:0] (
    .PACKAGE_PIN(iopin),
    .OUTPUT_ENABLE(dout_en),
    .D_OUT_0(dout),
    .D_IN_0(din)
);

(With iopin being the top-level module port.)

See the Lattice iCE40 technology library documentation for more details on SB_IO and other iCE40 primitives.