Suppose we have MSB_limit
and LSB_limit
. These two act as two flags and all bits between them (even the 1's - I think this simplifies the problem) must go to 1.
Is there a synthesizable solution to this?
Example to the problem:
MSB_limit = 7;
LSB_limit = 2;
//Let's suppose our register is 16bits, desired output:
0000000011111100
^ ^ ^ ^
| | | |
15 7 2 0 //positions
Easily achievable with for-loops:
SystemVerilog (IEEE 1800):
logic [N-1:0] my_reg;
always_comb begin
foreach(my_reg[idx])
my_reg[idx] = idx inside {[LSB_limit:MSB_limit]};
end
Verilog (IEEE 1364-2001 or greater):
reg [N-1:0] my_reg;
integer idx;
always @* begin
for (idx = 0; idx < N; idx=idx+1) begin
my_reg[idx] = (idx >= LSB_limit) && ( idx <= MSB_limit);
end
end
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