I have defined two modules, datapath and ctrl.
Then I define another module in the same file which instantiates both datapath and ctrl
module mult(input reset, input [3:0] i0,i1, output o);
wire [3:0] cnt, sh;
wire load, go,ld1
datapath d0(i0,i1,cnt,sh,load,go,o);
ctrl c0(reset, clk,sh,cnt,ld1,load,go);
endmodule
But verilog complains about "invalid module item" on the line "datapath d0...", WHY?
You are missing a semi-colon on the previous line.
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