24 bit counter state machine

Question

I am trying to create a counter in verilog which counts how many clock cycles there have been and after ten million it will reset and start again.

I have created a twenty four bit adder module along with another module containing twenty four D Flip flops to store the count of the cycles outputted from the adder.

I then want to have a state machine which is in the count state until ten million cycles have passed then it goes to a reset state.

Does this sound right? The problem is I am not sure how to implement the state machine.

Can anyone point me to a website/book which could help me with this?

thanks

Answer 1

As Paul S already mentioned, there is no need for a state machine if you want your counter to keep counting after an overflow. You can do something like this (untested, might contain typos):

module overflow_counter (
  clk,
  reset,
  enable,
  ctr_out
);

// Port definitions
input clk, reset, enable;
output [23:0] ctr_out;

// Register definitions
reg [23:0] reg_ctr;

// Assignments
assign ctr_out = reg_ctr;

// Counter behaviour - Asynchronous active-high reset
initial reg_ctr <= 0;
always @ (posedge clk or posedge reset)
begin
  if (reset)                 reg_ctr <= 0;
  else if (enable)
  begin
    if (reg_ctr == 10000000) reg_ctr <= 0;
    else                     reg_ctr <= reg_ctr + 1;
  end
end

endmodule

Of course, normally you'd use parameters so you don't have to make a custom module every time you want an overflowing counter. I'll leave that to you ;).

[Edit] And here are some documents to help you with FSM. I just searched Google for "verilog state machine":

• EECS150: Finite State Machines in Verilog
• Synthesizable Finite State Machine Design Techniques

I haven't read the first paper, so I can't comment on that. The 2nd one shows various styles of coding FSMs, among which the 3 always blocks style, which I highly recommend, because it's a lot easier to debug (state transitions and FSM output are neatly separated). The link seems to be down, so here is the cached Google result.