Is there a ifx-elsex statement in Verilog/SV like casex?

Question

Say I have a scenario in which I need to compare only a few bits of a register and I don't care about other bits. eq, I need to check the first and last bits of a 3 bit register (A[2:0]) and I don't care about the middle bit, say compare vector is 3'b1X0 (Parameter).

1. Simplest way to do this is choose all the bits I care about, AND them and I have generated a control signal: if ((A[2]==1) & ((A[0]==0)) Here the condition inside if statement is my control signal.

2. Another way is to use a casex statement: casex(A) begin 3'b1?0: ... , ... endcase.

3. Is there anything like ifx-elsex statement or something that can be used to do this kind of operation without using the 1st and 2nd method?

Thanks!

Answer 1

if (A[2:0] inside {3'b1?0} )

SystemVerilog keyword inside. It has been supported since at least Accellera's SystemVerilog 3.1 (before SystemVerilog was a part of IEEE). IEEE Std 1800-2012 11.4.13 has examples of use. inside is synthesizable.

There is also if ( A[2:0] ==? 3'b1?0 ) (IEEE Std 1800-2012 11.4.6). The only reference I have on hand (a book published 2004) says it is not supported for synthesis yet. You are welcome to try it.

Answer 2

(A[2]==1) is a logical expression the & is a bitwise operator, although either works it would be better semantics to use the && logical and operator. This is slightly different to most other languages where the && is a short-circuit operator.

Logically what you want is if ((A[2]==1) && ((A[0]==0)) but it could be reduced to a bitwise expression :

if ( ~A[0] & A[2] ) 

NB: Try to avoid using casex, the unknown parts will match x's in simulation. Try to use casez instead, ? can still be used to match don't cares.

Update comparing inside to casez

Case statements a clean control structure used in most languages to avoid large if elsif else chains. the inside operation will match x's to the do not care '?' values. this makes it usage similar to the casex which is considered to be bad practise to use as it can hide simulation fails.

casez(sel)
  4'b1??? a= 3'd4;
  4'b01?? a= 3'd3;
  4'b001? a= 3'd2;
  4'b0001 a= 3'd1;
  4'b0000 a= 3'd0;  
endcase

vs

if (sel inside {4'b1???})
  a= 3'd4;
else if (sel inside {4'b01??})
  a= 3'd3;
else if (sel inside {4'b001?})
  a= 3'd2;
...

The above is actually equal to the casex (but more verbose) I believe that instead of casex you could also use :

case(sel) inside
  4'b1??? a= 3'd4;
  4'b01?? a= 3'd3;
  4'b001? a= 3'd2;
  4'b0001 a= 3'd1;
  4'b0000 a= 3'd0;  
endcase

but then I would never use a casex.