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New posts in cpu-architecture

Is the TLB shared between multiple cores?

caching x86 cpu-architecture cpu-cache tlb

What is the relation between virt_to_phys and the CPU's MMU in the Linux kernel?

linux memory linux-kernel cpu cpu-architecture

CPU cache behaviour/policy for file-backed memory mappings?

c++ x86 operating-system cpu-architecture cpu-cache

What is the stack engine in the Sandybridge microarchitecture?

assembly x86 intel cpu-architecture

Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths

performance assembly x86 cpu-architecture perf

Game Boy: Half-carry flag and 16-bit instructions (especially opcode 0xE8)

assembly embedded emulation cpu-architecture gameboy

Why is ONE basic arithmetic operation in for loop body executed SLOWER THAN TWO arithmetic operations?

c++ performance assembly cpu-architecture google-benchmark

What does "store-buffer forwarding" mean in the Intel developer's manual?

assembly x86 intel cpu-architecture memory-model

Which cache mapping technique is used in intel core i7 processor?

x86 intel cpu-architecture cpu-cache amd-processor

What is the advantage of having instructions in a uniform format?

encoding cpu-architecture instructions fixed-width variable-length

Do sse instructions consume more power/energy?

performance x86 sse cpu-architecture energy

Why does this function run so much faster when it makes an extra read of memory?

performance assembly clang x86-64 cpu-architecture

Why denormalized floats are so much slower than other floats, from hardware architecture viewpoint?

floating-point cpu-architecture

How does CLFLUSH work for an address that is not in cache yet?

c linux-kernel intel cpu-architecture cpu-cache

Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?

performance x86 benchmarking intel cpu-architecture

Size of store buffers on Intel hardware? What exactly is a store buffer?

performance assembly x86 intel cpu-architecture

Real-world analog to TIS-100

cpu-architecture instruction-set stream-processing tis-100

OS X arch command incorrect [closed]

macos cpu-architecture

RISC-V: Immediate Encoding Variants

cpu-architecture riscv machine-code instruction-set immediate-operand

CPU and Data alignment

c alignment cpu-architecture processor
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