Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in cpu-architecture

Why are Intel x87 registers 80 bits wide?

assembly x86 intel cpu-architecture x87

What does "subsequent read" mean in the context of volatile variables?

java multithreading cpu-architecture

How does Spectre attack read the cache it tricked CPU to load?

security cpu cpu-architecture spectre side-channel-attacks

whats the purpose of x86 cr0 WP bit?

assembly x86 operating-system intel cpu-architecture

Definition/meaning of Aliasing? (CPU cache architectures)

caching architecture cpu-architecture cpu-cache

Are armv8 and arm64 the same?

ios xcode cpu-architecture arm64

Are loads and stores the only instructions that gets reordered?

x86 cpu-architecture memory-barriers

Does an x86 CPU reorder instructions?

multithreading assembly x86 cpu-architecture memory-barriers

Where is the Write-Combining Buffer located? x86

x86 intel cpu-architecture cpu-cache amd-processor

in what architectures/OS other thread can see default nonfinal field values after constructor call?

java multithreading constructor cpu-architecture memory-visibility

Intel CPUs Instruction Queue provides static branch prediction?

performance assembly x86 cpu-architecture branch-prediction

Can a TLB hit lead to page fault in memory?

memory-management operating-system kernel cpu-architecture tlb

Determining page numbers and offsets for given addresses

memory-management operating-system offset cpu-architecture virtual-memory

Why is a store-load barrier considered expensive?

multithreading concurrency cpu-architecture lock-free

Most portable library for dynamic code generation?

c++ assembly code-generation cpu-architecture machine-code

Is MOD operation more CPU intensive than multiplication?

c++ cpu-architecture multiplication division

Microarchitectural zeroing of a register via the register renamer: performance versus a mov?

assembly x86 x86-64 cpu-architecture

Out-of-order execution vs. speculative execution

cpu-architecture speculative-execution

How are MMIO, IO and PCI configuration request routed and handled by the OS in a NUMA system?

io x86 cpu-architecture numa
« Newer Entries Older Entries »