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New posts in vhdl

Does anybody have quantitative data on VHDL versus Verilog use?

comparison vhdl verilog

Assign a single bit from STD_LOGIC_VECTOR to STD_LOGIC

vhdl

VHDL difference between => and <=

syntax vhdl

How to declare an output with multiple zeros in VHDL

vhdl

What to use for VHDL/digital-logic simulation on Mac OS X

macos simulation vhdl digital-logic

Comparing a long std_logic_vector to zeros

vhdl

VHDL: use the length of an integer generic to determine number of select lines

generics vhdl

What does "others=>'0'" mean in an assignment statement?

if-statement process vhdl fpga

Where can I find a definitive list of the ModelSim error codes?

vhdl fpga modelsim

When should I use std_logic_vector and when should I use other data types?

integer port vhdl unsigned signed

Does VHDL have a ternary operator?

vhdl ternary-operator

Microcontroller + Verilog/VHDL simulator?

microcontroller simulator verilog vhdl

padding out std_logic_vector with leading zeros

vhdl

Can custom types be used in port declaration?

vhdl

How does signal assignment work in a process?

vhdl modelsim

Better ways to implement a modulo operation (algorithm question)

algorithm modulo vhdl

Why can't I increment this `std_logic_vector`

vhdl

VHDL: Using hex values in constants

hex vhdl constants

Concatenating bits in VHDL

concatenation vhdl

How to ignore output ports with port maps

port vhdl
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