How to declare an output with multiple zeros in VHDL

Question

Hello i am trying to find a way to replace this command: Bus_S <= "0000000000000000000000000000000" & Ne; with something more convenient. Counting zeros one by one is not very sophisticated. The program is about an SLT unit for an ALU in mips. The SLT gets only 1 bit(MSB of an ADDSU32) and has an output of 32 bits all zeros but the first bit that depends on the Ne=MSB of ADDSU32. (plz ignore ALUop for the time being)

entity SLT_32x is
   Port ( Ne : in  STD_LOGIC;
         ALUop : in STD_LOGIC_VECTOR (1 downto 0);
         Bus_S : out  STD_LOGIC_VECTOR (31 downto 0));
end SLT_32x;

architecture Behavioral of SLT_32x is
begin
  Bus_S <= "0000000000000000000000000000000" & Ne; 
end Behavioral;

Is there a way to use (30 downto 0)='0' or something like that? Thanks.

Answer 1

Try this: bus_S <= (0 => Ne, others => '0') It means: set bit 0 to Ne, and set the other bits to '0'.

Answer 2

alternative to the given answers:

architecture Behavioral of SLT_32x is
begin
  Bus_S <= (others => '0');
  Bus_S(0) <= ne;
end Behavioral;

Always the last assignment in a combinatoric process is taken into account. This makes very readable code when having a default assignment for most of the cases and afterwards adding the special cases, i.e. feeding a wide bus (defined as record) through a hierarchical block and just modifying some of the signals.