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Is there a VHDL equivalent to Verilog's @(*), i.e., automatic process sensitivity list

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vhdl

It is easy to update a combinatorial process and forget to update the sensitivity list. In Verilog the @(*) was introduced to say the sensitivity list is what is used in this process. Is there an equivalent in VHDL?

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Brian Carlton Avatar asked Mar 21 '11 22:03

Brian Carlton

People also ask

What is process sensitivity list in VHDL?

Sensitivity lists are parameters to a process which lists all the signals that the process is sensitive to. If any of the signals change, the process will wake up, and the code within it is executed. We've already learned to use the wait on and wait until statements for waking up a process when a signal changes.

What is a process's sensitivity list?

The sensitivity list identifies a set of signals that the process monitors for events. If the sensitivity list is omitted, the process should include one or more wait statements. On the other hand, if the sensitivity list is included, then the process body cannot include any wait statements.

What is a process in VHDL?

The process is the key structure in behavioral VHDL modeling. A process is the only means by which the executable functionality of a component is defined. In fact, for a model to be capable of being simulated, all components in the model must be defined using one or more processes.

What happens when sensitivity list does not have signal needed?

If a signal is in the sensitivity list of a process, the process will "wake up" and be evaluated whenever the value of that signal changes. If it is not in the sensitivity list, a signal can change, but a process will not be re-evaluated to determine what the new outputs should be.

3 Answers

I found this thread in comp.lang.vhdl. Sounds like VHDL-2008 adds wildcard sensitivity with process(all), but tool support varies.

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Andy Avatar answered Jan 18 '23 22:01

Andy

If you can not use VHDL-2008 yet, Sigasi HDT can automatically insert the correct sensitivity list for you.

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Hendrik Avatar answered Jan 19 '23 00:01

Hendrik

Emacs VHDL-mode can update them too. That's what I will go with.

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Brian Carlton Avatar answered Jan 18 '23 23:01

Brian Carlton
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