Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

Question

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution.

I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows:

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

I followed the project creation steps in the Altera tutorial, but when I try to compile the project I get the error:

Error (12007): Top-level design entity "alt_ex_1" is undefined

Answer 1

My problem was about verilog code compiler. But when I search for problem, I always saw this question. So I decided to add my solution too to guide others. It took me much time to find solution. here is what I had done to solve the problem.Just follow these steps (Quartus II 14.0.0) ; Assignments -> Settings -> Top-Level Entity ->Select your module

Answer 2

In chapter Starting a New Project, you were asked to call your project light. It seems to me that you didn't follow that step correctly and name your project alt_ex_1. That's why you're getting 12007 error, since the compiler has no idea what is the top-level entity in you design.

To solve that problem you can:

1. Change the top-level entity assignment in Assignments -> Device -> General.
2. Set your module as top-entity via Project Navigator (Files -> Set as top-level entity).

Btw 1, 2, 3, ... - all about the same problem.