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I've been having some issues with some VHDL code I wrote (see my other question for details if you're curious: VHDL integer'image Returns "0"). I need some way to see what is happening to my variables. Everything I read seems to indicate that I should be able to use the 'report' statement to see some output, but nothing I've read tells me where I would see this output.
So my question is this:
I'm writing VHDL code and programming an Altera DE2 FPGA board... Can I use the report statement to get some output, and if so, how? Currently I'm using Altera's Quartus II software. I tried to install ModelSim, but the student edition does not seem to work on Windows 7 (I can't even get an installer to show up... running the setup just leaves a dangling process).
Thanks!
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The basic syntax of a report statements in VHDL is: report <message_string> [severity <severity_level>]; The message string obviously has to be a string. The severity level has the datatype std.standard.severity_level . Possible values are: note, warning, error, failure.
The REPORT statement defines the type and characteristics of a report. Multiple reports can be specified per single JOB Activity Section. REPORT statement with its parameters is placed at the end of each JOB Activity Section.
What is the use of assert statement in VHDL? Explanation: ASSERT statement is used to check the consistency of the program. It checks a condition and generates a message which is printed on the screen depending on the status of the condition whether it is true or false.
The report statement prints its output to the console of your simulator. If you work with Altera, you probably want to the ModelSim version that they ship.
a := 5;
report "The value of 'a' is " & integer'image(a);
People also use wave traces to debug their code. But you also need your simulator for that.
You'll need to find a way to get ModelSim installed on your Windows 7.
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Both Philippe and Martin have provided excellent answers to your question, but I want to emphasize an important aspect of what VHDL is. VHDL is a tool that serves two quite different purposes.
On one side it is an behavioral modeling language for describing concurrent systems. Your model is compiled into an executable and runs on your computer. This is what we refer to as a simulator. It let's you inspect the model during various states of the execution and makes it easy to debug your design before you go to the next step: Implementation.
VHDL is also used as a meta-language for describing a hardware architecture, known as RTL. This description is translated into a list of primitives supported by your architecture (synthesis), and then placed and routed into a physical device.
It's important to understand the difference between these two uses to take full advantage of the language. Happy coding!
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REPORT prints to the console of the simulator.
Modelsim in GUI mode has a console window. If console mode, it's erm, just a console anyway!
GHDL is also console mode only, so it'll come up in your terminal/CMD window when you run the simulation.
What REPORT can't do is print messages out from the synthesized code.
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