Using entities from another file in VHDL

Question

How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file? Here is what I have but it is not right:

updated code:

library ieee;
use ieee.std_logic_1164.all;
library Part2;
use Part2.all;


entity problem4Gates is
    port(X,Clk: in std_logic; Q: out std_logic_vector(2 downto 0)) ;
end entity problem4Gates;  

architecture behavioral OF problem4Gates IS  

for all: yourGateName use entity  Part2.JKflipFlop(jkFF); --port (J, K, Clk, Preset, Clear : in std_logic; Q, Qn : Buffer std_logic) --JKflipFlop --jkFF    
signal s0, ns0, s1, ns1, s2, na2, ps0, ps1, ps2, restart : std_logic :='0';
begin
    process(clk)
    begin                  
         yourgatename( ns0, clk, '0', restart, Q(0), ns0 );
    end process;
end architecture behavioral;

I now get 2 errors:

# Error: COMP96_0078: Part3.vhd : (13, 10): Unknown identifier "yourGateName".
# Error: COMP96_0134: Part3.vhd : (13, 10): Cannot find component declaration.

Answer 1

How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file?

You don't "include a file". VHDL is not C.

If you compile several different architectures of a particular entity they can all be in one file, even the same file as the entity, or they can be scattered across multiple files.

You can then make use of them - the easiest way is direct instantiation. In the higher-level architecture, you do:

inst_of_one_arch     : entity work.some_entity(one_arch) port map....
inst_of_another_arch : entity work.some_entity(another_arch) port map....

There are other ways, but they can be a lot of hassle.