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Suppose you have a loop
for i in 1 downto 0 loop
for j in 1 downto 0 loop
tS0 <= i;
But I need to convert the integer (which is natural) to std_logic. tS0 is declared as std_logic. I am only doing it one bit (0 or 1). That is, my i and j can only represent the value {0,1}.
I think I am heading to the wrong approach here. Can someone please tell me what should I do instead?
I don't think std_logic has to_unsigned method. i tried letting tS0 to be a vector (1 down to 0), and assigned like tS0(0) <= i, and etc. But it still didn't work out.
Thank you very much!
885
function conv_std_logic_vector(arg: std_ulogic, size: integer) return std_logic_vector; These functions convert the arg argument to a std_logic_vector value with size bits. If arg is unsigned or positive, it is treated as an unsigned value; if it is negative, it is converted to 2's complement signed form.
Std_logic signals represent one data bit and std_logic_vector represents several data bits. The signal assignments for standard logic and standard logic vector data types are shown in Example 1-15. The number of data bits for a std_logic_vector is defined in the signal assignment statement.
-- Id: D. 3 function TO_UNSIGNED ( ARG,SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (SIZE-1 downto 0) -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with -- the specified SIZE.
Both std_logic_vector and unsigned are unconstrained arrays of std_logic . As is the signed type. std_logic_vector is declared in the std_logic_1164 package; unsigned and signed are declared in the package numeric_std .
There is no need to convert from integers. You can just iterate over the std_logic datatype:
for i in std_logic range '0' to '1' loop
ts0 <= i;
end loop;
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