VHDL assigning literals

Question

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

variable LCD_DATA: unsigned(19 downto 0) := 0;

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

Answer 1

See other answers, and note that for non-zero literals, you probably want to do something like:

variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, 20);

Substitute a literal for n. This works for n=0 too, of course, but it's not as tidy as (others => '0').

Answer 2

--Either 
variable LCD_DATA: unsigned(19 downto 0) := (others => '0');
--Or you can also write it like 
variable LCD_DATA: unsigned(19 downto 0) := "00000000000000000000";

And for the 2nd part of your question while adding number of this type.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

Check whether you have used above libraries in the code or not.