I have two 2D arrays:
type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
type array2D is array (0 to 10, 0 to 10) of std_logic; -- Real 2D array
How do I access the range of the std_logic_vectors
in the former and the range in the latter? I could of course use a variable to keep track of their size but I would prefer to avoid that. I am trying to loop over the arrays using GENERATE
statements.
array1x1D:
VHDL-2002: A subtype is required for the std_logic_vector(0 downto 10)
if you
want to get the range of this part, thus splitting the type into:
subtype array1x1D_element is std_logic_vector(0 to 10);
type array1x1D is array (0 to 10) of array1x1D_element; -- Array of arrays
Then you can do array1x1D_element'range
.
VHDL-2008: Use the added 'element
attribute (probably for that purpose :-),
and write array1x1D'element'range
.
array2D:
Access the different dimensions through an index to 'range
, thus
with array2D'range(1)
and array2D'range(2)
.
entity test1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a1 of test1 is
type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
type array2D is array (0 to 10, 0 to 5) of std_logic; -- Real 2D array
signal s1 : array1x1D;
begin
name : process is
begin
report "array1x1D(0)'length:" & integer'image(s1(0)'length);
report "array2D'length(1):" & integer'image(array2D'length(1));
report "array2D'length(2):" & integer'image(array2D'length(2));
wait;
end process name;
end architecture a1;
produces:
# run -all
# ** Note: array1x1D(0)'length:11
# Time: 0 ns Iteration: 0 Instance: /test1
# ** Note: array2D'length(1):11
# Time: 0 ns Iteration: 0 Instance: /test1
# ** Note: array2D'length(2):6
# Time: 0 ns Iteration: 0 Instance: /test1
#
I can't immediately see a way to figure out the length of the vector elements of the 1d array without an intermediate signal/constant/variable of that type...
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