Morten Zilmer questions

Morten Zilmer answers

• Do all Flip Flops in a design need to be resettable (ASIC)?
• Function with don't-care inputs
• vhdl "for loop" with step size not equal to 1
• vhdl subtract std_logic_vector
• VHDL unsigned vector vs integer comparison
• How to declare output array in VHDL?
• difference between using reset logic vs initial values on signals
• How good are VHDL's random numbers?
• Alternative method for creating low clock frequencies in VHDL
• VHDL synthesis of if statements without elsif and else condition