Morten Zilmer questions

Morten Zilmer answers

• Why can't I call a function in a constant declaration, that is defined in the same package in ModelSim?
• Optional PORTs in VHDL?
• VHDL what is more efficient to use : an integer with range or a std_logic_vector
• How to generate .rbf files in Altera Quartus?
• Target (variable "") is not a signal error in VHDL
• Do all Flip Flops in a design need to be resettable (ASIC)?
• Function with don't-care inputs
• vhdl "for loop" with step size not equal to 1
• vhdl subtract std_logic_vector
• VHDL unsigned vector vs integer comparison