VHDL unsigned vector vs integer comparison

Question

In vhdl, assume I have an unsigned vector defined as follows:

signal s_col_rd_check : unsigned(7 downto 0);

Now, whether I use the following library,

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Or the following

use ieee.numeric_std.all;

Can I use do a comparison between my unsigned vector and an integer value as follows?

some_assignment <= '1' when (s_col_rd_check < 190) else '0';

where 190 is just an integer. Will the above comparison be the same whether I use either one of the libraries?

Thanks, --Rudy

Answer 1

The ieee.std_logic_arith and ieee.std_logic_unsigned are proprietary Synopsys packages, and not defined as part of the IEEE VHDL standard. So it is misleading that these packages use the ieee library name, since they are not defined as part of the IEEE standard.

A quick Google search for "std_logic_arith.vhd" yielded at least three different versions of the package, so the answer to your question may depend on which version of the proprietary package your are using... which is a strong indication, that using these proprietary packages is not the right approach, if you want to have well-defined and identical behavior of the design across different tools.

So the reliable approach is to use only the ieee.numeric_std, which is part of the IEEE VHDL standard, thus having well-defined behavior.

And with use ieee.numeric_std.all;, you can do the comparison in:

some_assignment <= '1' when (s_col_rd_check < 190) else '0';

since ieee.numeric_std defines the function:

function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;