Target (variable "") is not a signal error in VHDL

Question

I have this piece of code

  function func (k1, k2 : in bit_vector) return bit_vector is

    variable result : bit_vector(1 to 32);

    begin
        for i in 0 to 31 loop
            result(i) <= k1(i);
        end loop;

        return result;
    end func;

I get this error :

target (variable "result") is not a signal

I know I need to change the type of result but I don't know what it should be. Thanks.

Answer 1

When assigning to a variable use := as:

result(i) := k1(i);

Assign with <= is for assign to signal.

The range of result (1 to 32) does not match the range in the loop (0 to 31), so first assign in the loop (result(0) := k1(0)) will cause in a range error. Fix this by changing either result or loop range.