What is "gate count" in synthesis result and how to calculate

Question

I'm synthesizing my design with design compiler and have some comparison with another design (as a evaluation in my report). The Synopsys's tool can easily report the area with command but in all paper I've read care about gate count.

My quiz is what is gate count and how to calculate it?

I googled and heard about gate count is calculated as total_area/NAND2_area. So, is it true?

Thank for your reading and please don't blame me about stupid question :(.

Answer 1

Synthesised area is often quoted as Gate count in NAND2 equivalents. You are correct with:

(total area)/(NAND2 area).

Older tools and libraries use to report this number, a few years a go I noticed a shift for tools to just provide areas in Square Microns. However the gate count is a nicer number to get your head around, and the number is portable between different size geometries.

40K for implementation A is smaller than 50K for implementation B. Much harder to compare 100000 um^2 for implementation A process X vs 65000 um^2 for implementation B on process y.