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Equivalent of #ifdef in VHDL for simulation/synthesis separation?

Tags:

vhdl

In order to ease the visual reading of simulation waves, I would like to assign some signals to "XXXX", but only at simulation time, and thus I want the logical synthesis tool (ISE in my case) to skip those instructions.

Two questions from here:

  1. Is there an equivalent technique of a #ifdef SIMULATION_TIME, like in C ?
  2. Would an assignment to "XXXX" have any influence on the logical synthesis (reset to 0 ? warnings ? nothing ?). If it has no impact at all, then my question is answered. If not, I still need to assign to "XXXX"...

Thanks.

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Aurelien Ribon Avatar asked Feb 25 '11 14:02

Aurelien Ribon

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1 Answers

(1) You're looking for

--pragma synthesis_off
  -- your simulation-only code
--pragma synthesis_on

(2) You might get some warnings from ISE, especially when these signals drive logic. Just make sure, that the signals have a defined value before you use them. This method should work then, as well.

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Deve Avatar answered Oct 03 '22 11:10

Deve
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