What is the purpose of the `std_logic` enumerated type in VHDL?

Question

What is the purpose of the std_logic enumerated type?

'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care. 

Answer 1

• 'X' usually is caused by two statements driving the same signal in opposite directions,i.e., '0' and '1'
• 'Z' is used to build a tri stated output/input
• 'L' and 'H' are used to model a pulldown or pullup respectively
• '-' is used in comparisons when you don't care about certain bits in a vector

Answer 2

std_logic is basically a single wire or bit. You can use logical operators (and, or, xor, etc.) on them. When simulating a design I believe I have only seen 'X', '0', or '1'. Obviously you want '0' or '1'. An 'X' indicates that the value is unknown (possibly not connected to anything or there is a glitch in the signal). Also, std_logic_vector can be used for signals that need to be more than 1 bit wide. I'm not sure if this answers your question...