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What is the purpose of the `std_logic` enumerated type in VHDL?

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vhdl

digital

What is the purpose of the std_logic enumerated type?

'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care.
like image 908
newprint Avatar asked Sep 20 '12 01:09

newprint

People also ask

What is std_logic?

Std_logic signals represent one data bit and std_logic_vector represents several data bits. The signal assignments for standard logic and standard logic vector data types are shown in Example 1-15. The number of data bits for a std_logic_vector is defined in the signal assignment statement.

What is the difference between std_logic vs Std_ulogic data type?

VHDL includes few built-in types but offers several additional types through extension packages. Two of the most widely used types are std_logic and std_ulogic . The difference between them is that the former is resolved while the latter isn't.

What does STD stand for in VHDL?

'std' stands for 'standard', in reference of the Standard Package. Source: https://www.csee.umbc.edu/portal/help/VHDL/stdpkg.html.

2 Answers

  • 'X' usually is caused by two statements driving the same signal in opposite directions,i.e., '0' and '1'
  • 'Z' is used to build a tri stated output/input
  • 'L' and 'H' are used to model a pulldown or pullup respectively
  • '-' is used in comparisons when you don't care about certain bits in a vector
like image 118
BennyBarns Avatar answered Sep 22 '22 08:09

BennyBarns

std_logic is basically a single wire or bit. You can use logical operators (and, or, xor, etc.) on them. When simulating a design I believe I have only seen 'X', '0', or '1'. Obviously you want '0' or '1'. An 'X' indicates that the value is unknown (possibly not connected to anything or there is a glitch in the signal). Also, std_logic_vector can be used for signals that need to be more than 1 bit wide. I'm not sure if this answers your question...

like image 28
Robert Harris Avatar answered Sep 24 '22 08:09

Robert Harris
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