Graph/schematic generator for VHDL

Question

I have a VHDL project that consists of a top level module containing other modules interconnected in various ways (and some of these modules are, themselves, containers for other modules).

Is there a utility that can generate a schematic illustrating the relationships between the modules? I'm not concerned with configuration details or architecture, just the inputs, outputs and nesting for each module in my project.

Answer 1

Xilinx PlanAhead has a very nice schematic viewer, which you can run at various stages of the implementation (i.e. post RTL analysis, post-synthesis, post-place and route). Here's what it looks like: