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Way to initialize synthesizable 2D array with constant values in Verilog

in VHDL, I can easily do this:

constant    cmdbytes       : bytearray(0 to Total) := (x"05", x"00", x...};

I want synthesizable constants so that when the FPGA starts, this array has the data I supplied. These registers are wired to VCC or ground to represent 1 or 0. I can then use them to generate a waveform. Also I would like to have 2D byte array which is 3D in verilog world.

like image 316
Hai Bi Avatar asked Jan 02 '13 22:01

Hai Bi


2 Answers

If you're just using the array to pull out one value at a time, how about using a case statement? Granted, it's a long-winded way of doing it, but you could always write a script to write the RTL for you.

reg [7:0] value;
reg [7:0] i;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        i <= 8'd0;
    else
        i <= i + 1;
end

always @(*) begin
    case(i) 
        8'h00: value = 8'd0;
        8'h01: value = 8'd34;
        ...
    endcase
endcase

Another way is to use an initial statement. As far as I'm aware, FPGA synthesis tools will allow you to set initial values for arrays in the following manner. Again, a script to write this may be the way to go.

reg [0:35][7:0] my_array;

initial begin
    my_array[0] = 8'd45;
    my_array[1] = 8'd26;
    ...
end

And if your FGPA synthesis tools support some SystemVerilog, you'll be able to initialise the array like so:

reg [0:34][7:0] my_array = '{ 8'd90, 8'd34, ... }; // note the '{
like image 112
Marty Avatar answered Sep 28 '22 13:09

Marty


module test (

   input [7:0]   p1_sa,            // i
   input [7:0]   p1_sb,            // i
   output [7:0]   p3,            // o
   output [7:0]   p3b            // o
);

logic [7:0] array2d [7:0] = {99,124,119,123,242,107,111,197};

   assign p3    = array2d[p1_sa];
   assign p3b   = array2d[p1_sb];

endmodule

I tried the above system verilog code and it is working fine in modelsim and Vivado.

like image 30
user3702551 Avatar answered Sep 28 '22 13:09

user3702551