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Can some one explain why the golden rule when writing VHDL is that the if-then-else statement must be in a process. Is it because inside the process, the statements are executed sequentially, while outside they're not.
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An if…else statement is a sequential statement in VHDL which got executed depending on the value of the condition. The if condition tests each condition sequentially until the true condition is found.
Explanation: Since the condition under IF is true so the statements under IF will be executed and hence output will be assigned the value of signal a. Though the condition under ELSIF is also TRUE but IF has the highest priority so all the following ELSIFs will be ignored. This is the problem in IF statement.
Syntax. If the Boolean expression evaluates to true, then the block of code inside the 'if' statement will be executed. If the Boolean expression evaluates to false, then the first set of code after the end of the 'if' statement (after the closing curly brace) will be executed.
The simple answer is "because that's how the syntax of the language is"!
If you want to select from some options with code not in a process you can do:
sig <= a when sel = 1 else
b when sel = 2 else
default_value;
or
with sel select
sig <= a when 1,
b when 2,
default_value when others;
See here for many examples of a mux
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