Purpose to providing more than one architecture?

Question

I'm in the process of learning VHDL and I'm trying just learning from examples, syntax guides, and experiments.

One thing I don't quite understand is why you'd ever want to provide more than one architecture. For instance, this example MUX code:

architecture behv1 of Mux is
begin
    process(I3,I2,I1,I0,S)
    begin

        -- use case statement
        case S is
        when "00" =>    O <= I0;
        when "01" =>    O <= I1;
        when "10" =>    O <= I2;
        when "11" =>    O <= I3;
        when others =>  O <= "ZZZ";
    end case;

    end process;
end behv1;

architecture behv2 of Mux is
begin

    -- use when.. else statement
    O <=    I0 when S="00" else
        I1 when S="01" else
        I2 when S="10" else
        I3 when S="11" else
        "ZZZ";

end behv2;

Is there a purpose for it, or is it just for example sake?

Also, not sure if this belongs here or Electronics.SE, so figured I'd try here first.

Answer 1

While that particular example seems to be just for an example's sake, there are several reasons why you'd want different architectures for some designs.

One thing that is commonly done is to provide black box models of IP designs for performance reasons, when you are trying to simulate another (unrelated) part of the whole SoC design.

Or, you might have a higher level model of the IP that allows faster simulation times, as well as the model intended for synthesis. Higher level models are often used for processor cores, since simulating the entire core is usually not necessary when verifying the rest of the design.

Another possible reason is to selectively have different behavior in an IP design so that slightly different versions can be instantiated when the IP is integrated into a SoC design. For example, one architecture might be intended for one-clock-domain operation while another might have synchronization between two different clock domains.